Setup and Hold time for flip flops

The most frequently asked question in the interview is regarding the timing of flops. Generally the questions asked are based on calculation of minimum time cycle (max. frequency), setup slack and hold slack. 

Consider a D –type edge-triggered, Flip Flop (FF). The time just before and just after the clock edge, is the critical time, where the D input must not change.

Region just before the clock is setup time (t_setup).

Region after the clock edge is hold time (t_hold).

Every flip flop has minimum required values for t_setup and t_hold. The values of t_setup and t_hold vary strongly with temperature, voltage and process.

What happens to Q if D input changes within the t_setup and t_hold window?

• Q may follow D correctly.
• Q may follow D incorrectly.
• Q may assume a metastable state for an indeterminate time followed by a transition to logic 1 or logic 0.

For correct operation, D inputs must be stable for t_setup prior to clock and stay stable for a t_hold afterwards.

Minimum Cycle Time:

Time taken by data to travel from one flop to another flop. Path between two flops is composed of :

• Clock to Q delay (t_clk-q).
• Propogation delay through the combo logic. (tcombo).
• The required setup time (t_setup) of FF1.

  

        t_min  = t_clk-q + t_combo + t_setup 

f_max = 1/t_min

Setup Slack:

The setup time is a function of the clock period, combo delay and the clk-to-output delay.

Actual t_setup = t_clk – t_clk-q - t_combo

As said earlier, each flop has a minimum specified t_setup.

The difference between the actual setup time and the minimum required setup time is known as setup slack.

Setup Slack = Actual t_setup – Reqd. t_setup

A positive slack is always desirable. 

For maximum frequency, the setup slack is zero.

Hold Time:

Hold time is the amount of time that FF0’s old data must persist at the D input of FF1, i.e. D1 after the clock edge.

Actual hold time = t_clk-q + t_combo.

Each flop has a minimum specified t_hold. The difference between the actual hold time and the minimum required hold time is known as hold slack.

Hold slack = Actual hold time – Reqd. t_hold 

For examples, please visit Setup and Hold time for flip flops - Part 2
For Verilog timing tasks related to setup and timing checks,  please go through this link.