CMOS Interview Questions - v1.2

Q.1) Draw the CMOS layout of tristate buffer.

Answer) When En = 0,
              The PMOS part of the circuit as well as NMOS part of the circuit doesn't conduct, so therefore no one drives the output, resulting in high impedance circuit.

              When En = 1; In = 0,
              The PMOS part of the circuit conducts resulting in '1' at the output.
 
              When En = 1; In = 1,
              The NMOS part of the circuit conducts resulting in '0' at the output.

Q.2) Draw the CMOS layout for the following function :
         z = [a.b +c.(d + e)]

Answer) From CMOS Interview Questions - v1.1 post, the key to solving such problems is that first derive the PMOS part (pullup circuit) and NMOS part (pulldown circuit) circuit and then draw the complete CMOS layout.

PMOS Part  = not([a.b + c.(d+e)]
                    = not(a.b).not(c.(d+e))
                    = (not(a) + not(b)).(not(c) + not(d).not(e))

NMOS Part = (a.b + c.(d+e))

Q.3) Explain transmission gate.

Answer) A transmission gate, or analog switch, is defined as an electronic element that will selectively block or pass a signal level from the input to the output. This switch is comprised of a pMOS transistor and nMOS transistor. The control gates are biased in a complementary manner so that both transistors are either on or off.

When the voltage on node X is a '1', the complementary '0' is applied to node active-low X, allowing both transistors to conduct and pass the signal at A to B. Similarly, when the voltage on node active-low X is a '0', the complementary '1' is applied to node A, turning both transistors off and forcing a high-impedance condition on both the A and B nodes.

The labels A and B can be reversed.

Q.4) Draw 2-to-1 mux using transmission gate.

Answer)

Q.5) Draw the layout of XOR gate using transmission gate.

Answer)