VHDL Interview Questions - v1.0

Q.1) What is VHDL?

Answer) VHDL stands for "VHSIC Hardware Description Language." VHSIC, in turn, stands for "Very High Speed Integrated Circuit," which was a U.S. Department of Defense program.

Q.2) Difference between VHDL and VERILOG?

Answer) 

	VHDL	Verilog
Compilation	Multiple design-units (entity/architecture pairs), that reside in the same system file, may be separately compiled if so desired. However, it is good design practice to keep each design unit in its own system file in which case separate compilation should not be an issue.	Care must be taken with both the compilation order of code written in a single file and the compilation order of multiple files.  Simulation results can change by simply changing the order of compilation.
Data Types	VHDL may be preferred because it allows a multitude of language or user defined data types to be used.	Verilog data types are very simple, easy to use and very much geared towards modeling hardware structure. Unlike VHDL, all data types used in a Verilog model are defined by the Verilog language and not by the user
Design reusability	VHDL. Procedures and functions may be placed in a package so that they are available to any design-unit that wishes to use them.	There is no concept of packages in Verilog. Functions and procedures used within a model must be defined in the module.  To make functions and procedures generally accessible from different module statements the functions and procedures must be placed in a separate system file and included using the `include compiler directive.
	VHDL is strongly typed.	Verilog is loosely typed.
	VHDL is case insensitive.	Verilog is case sensitive.
	Supports library management.	No support for librariers.

Q.3) Difference between SIGNAL and VARIABLE ?

Answer)

	Signal	Variable
Assignment	<=	:=
Utility	Represents circuit interconnects (wires)	Represents local information.
Scope	Can be global (seen by entire code)	Local (visible only inside the corresponding PROCESS, FUNCTION or PROCEDURE)
Behaviour	Update is not immediate n sequential code(new value generally available at the end of PROCESS, FUNCTION or PROCEDURE)	Updated immediately (new value can be used in next line of code)
Usage	In a PACKAGE, ENTITY or ARCHITECTURE. In an ENTITY, all PORTS are SIGNALS by default.	Only in sequential code, that is in PROCESS, FUNCTION or PROCEDURE

Q.4) Are Verilog/VHDL concurrent or sequential language in nature?

Answer)

• Verilog and VHDL both are concurrent languages. 
• Any hardware descriptive language is concurrent in nature.

Q.5) Describe the logic system introduced by the IEEE 1164 standard.

Answer) IEEE 1164 standard describes a 9-value logic system.

• 'U' : unresolved
• 'X' : Forcing unknown
• '0' : Forcing low.
• '1' : Forcing high.
• 'Z' : High impedance.
• 'W' : Weak unknown.
• 'L' : Weak low.
• 'H' : Weak high.
• '-' : Don't care.